The decrease in cost of nonvolatile memory devices has contributed to a recent explosion in demand for portable electronic devices. Although electronically-erasable nonvolatile memory (hereinafter “FLASH memory”) has been commercially available, recent advances in memory cell and transistor technology have allowed for a proliferation of consumer devices that store large amounts of information, such as high-resolution digital cameras, portable digital video recorders, and personal music players, which can store large amounts of pictures, videos, and songs, respectively.
Two types of FLASH memory have emerged in response to this demand: “NOR” technology, which employs a parallel memory cell architecture, and “NAND” technology, which employs a serial memory cell architecture. Each type of FLASH memory is well-suited to certain consumer applications. For example, NAND technology may be beneficial where storage density and cost are important considerations, such as music and video storage applications. By contrast, NOR technology may be beneficial where access time is an important consideration, such as software storage and execution.
Memory capacity in nonvolatile memory devices in general, and NAND memory devices in particular, has increased along with consumer demand for ever-increasing amounts of storage in portable electronic devices. Demand for increased memory capacity has led to greater memory array densities and different memory architectures. Yet, as memory array densities continue to increase, parasitic effects have emerged, which tend to limit further increases in memory array densities and limit application of different memory architectures to meet consumer demand. Parasitic effects can lead to an inability to correctly read stored data from the FLASH memory, as discussed below.
FIG. 1A illustrates a cross-sectional view of a conventional stack of memory cells 100. This stack 100 is depicted as a NAND stack of Charge-Trapping type (“CT-NAND” stack) in which charges are trapped into a gate insulating film. As illustrated, stack 100 comprises a series of transistors with shared diffusion regions present in p-well 102, including diffusion regions 104, 106, 108, 110, 112, 114, and 116. These shared diffusion regions contribute to formation of memory cells 132, 134, 136, and 138, as well as formation of source selector 130 and drain selector 140. Drain 116 is coupled to a global bitline by drain contact 120 and source 104 is coupled to a shared source line by source contact 118. Additionally, as illustrated, each transistor in FIG. 1 comprises a gate, a gate oxide further comprising a charge-trap region, and isolation oxides on the left and right sides of the gate oxide (in this cross-sectional view). As illustrated, for example, source selector 130 comprises gate oxide 130a further comprising charge-trap region 130b, gate 130c, isolation oxide 130d, and isolation oxide 130e, and memory cell 132 comprises gate oxide 132a further comprising charge-trap region 132b, gate 132c, isolation oxide 132d, and isolation oxide 132e. 
FIG. 1B illustrates a biasing configuration for a stack of memory cells 150 during a conventional erase operation. During a conventional erase operation, the gates of memory cells within the stack are biased at ground and p-well 102 is biased at a high voltage, thereby creating a voltage differential across the oxide of the memory cells that is large enough to tunnel stored electrons from the charge-trap regions within the memory cells to p-well 102. As illustrated in FIG. 1B, gates 132c, 134c, 136c, and 138c are biased to ground (0 Volt) during a conventional erase operation, while p-well 102 is biased to Verase. Additionally, during a conventional erase operation, source selector 130 and drain selector 140 are configured with their gates in floating states. As illustrated in FIG. 1B, the gates of selectors 130 and 140 are electrically floating. The floating states of gates of the selectors can lead to those gates capacitively coupling to the high voltage bias on p-well 102. Thus, the bias on the gates of selectors 130 and 140 may be substantially similar to Verase during an erase operation.
Another type of NAND memory device, i.e., a floating gate type, is well known in the art. This type of NAND memory device is called “FG-NAND,” in contrast to CT-NAND. In FG-NAND memory devices, memory cells in a NAND stack include a floating gate and a control gate provided over the floating gate, and each of source and drain selectors sandwiching a plurality of memory cells therebetween is constructed to operate as a single gate transistor by short-circuiting the floating and control gates to each other. U.S. Pat. No. 7,924,622 B2 discloses an erase operation for such FG-NAND memory devices.
The inventors of the present invention recognize that in CT-NAND memory devices, parasitic effects can arise from these biasing conditions, because voltage differentials between gates of the selectors and gates of memory cells adjacent to the selectors can be sufficient to tunnel electrons into isolation oxides associated with memory cells adjacent to the selectors. Referring again to FIG. 1B, for example, the floating state of gate 130c, which may lead to a bias of Verase on gate 130c, and the grounding of gate 132c within memory cell 132, may lead to a voltage differential of Verase between gate 130c and gate 132c. This voltage differential may be sufficient to tunnel electrons into isolation oxide 132d. 
If electrons tunnel into an isolation oxide, such as isolation oxide 132d, they may become trapped. If electrons become trapped in sufficient number within an isolation oxide, those trapped electrons can interact with the electric field that exists within a memory cell during a read operation by reducing or eliminating that electric field. Therefore, electron trapping in an isolation oxide of a memory cell, such as electron trapping in isolation oxide 132d of memory cell 132 (near selector 130), can have the effect of raising the threshold voltage of that memory cell (such as memory cell 132 in this example). In sufficient quantity, electron trapping in an isolation oxide can have the detrimental effect of reducing or eliminating channel formation and thus reducing or eliminating conduction within a memory cell during a read operation. Such changes to the conduction of a memory cell within a stack of memory cells can lead to the effected memory cell incorrectly being read as a programmed memory cell rather than an erased memory cell. Thus, these parasitic effects can lead to an inability to correctly read data within the FLASH memory device.
Additionally, unlike a conventional erase operation occurring in a memory cell rather than a selector, this accumulation of electrons in an isolation oxide is irreversible; i.e., the accumulation of electrons cannot be offset by an erase operation. This inability to reverse electron trapping in isolation oxides, such as isolation oxide 132d of memory cell 132, is due to the electrons in the isolation oxide being introduced by an erase operation. Thus, the means for removing electrons from a location where they are trapped—normally an erase operation—could only tend to increase the number of electrons trapped in the isolation oxide. Accordingly, accumulation of electrons in an isolation oxide, such as isolation oxide 132d, may be permanently detrimental to operation of a FLASH memory device because removal of the trapped electrons may not be possible once they have accumulated. This condition represents a serious parasitic effect that designers of modern NAND FLASH memory devices have faced.
Accordingly, a need exists for methods that reduce or avoid the parasitic effects noted above, while allowing further improvements in memory array density and alternative geometries for NAND FLASH memory devices.